Complex programmable logic devices (CPLDs), in contrast to field programmable gate arrays (FGPAs), use programmable AND arrays and macrocells to form sum-of use programmable AND arrays and macrocells to form sum-of-product representations of logical functions desired by a user. In addition, to performing a desired logical function, users of CPLDs may also require memory functions in applications such as ATM cell processing, clock domain buffering, shift registers, finite impulse filter delay lines, or program memory. The amount of memory a user will require depends upon the particular application—some require more memory storage and others require less. Thus, it is desirable to provide CPLDs with flexible memory structures to satisfy the majority of users.
To meet the need for a CPLD having a memory capability configurable according to an individual users needs, co-owned U.S. Ser. No. 10/133,016, (the '016 application) filed Apr. 26, 2002, discloses a programmable logic device having logic blocks that may be reconfigured to perform memory functions. The programmable AND arrays within a CPLD includes fuse points that control whether input signals affect the product term outputs. As disclosed in the '016 application, the fuse points within a programmable AND array may be configured for use as a memory array. The '016 application is hereby incorporated by reference in its entirety. The '016 application claims the benefit of co-owned U.S. Provisional Patent Application No. 60/356,507, entitled “DEVICE AND METHOD WITH GENERIC LOGIC BLOCKS,” filed on Feb. 11, 2002.
Although the programmable device disclosed in the '016 application permits a user to reconfigure logic blocks to perform memory functions, the reconfigured logic blocks are no longer available to a user to perform desired logical functions. Should a user implement a shallow and widely distributed memory within such a programmable device, valuable logic resources may be depleted.
Accordingly, there is a need in the art for an improved programmable device architecture providing flexible memory capability.